1. Field of the Invention
The present invention relates to a data transfer device, a semiconductor integrated circuit, and a processing status notification method for controlling transfer of data.
2. Description of the Related Art
As the processing capability of computers has been improving in recent years, the amount of data used by computers is constantly ballooning, and storage for storing massive amounts of data is being studied. Specifically, a technology has been established called RAID (Redundant Array of Independent Disks) for example, whereby a disk system which realizes high speed, great capacity, and high reliability, can be constructed by combining multiple had disk drives.
In disk systems such as the aforementioned RAID and so forth, a disk array device having multiple disks for storing data accepts commands from a host computer or the like which is a higher-level device, whereby writing (write) and reading (read) of data is performed. At this time, in general arrangements, the data exchanged between the computer and disks is cached in cache memory within the disk array device, and subsequently is read out from this cache memory, in order to attain higher speeds. Also, the host computer is connected to a channel adapter within the disk array device, and data transfer is executed between the host computer and cache memory and disks via this channel adapter.
The channel adapter has a DMA chip such as an LSI (Large Scale Integration) for controlling data transfer by direct memory access (hereafter abbreviated as “DMA”), with the DMA chip executing data transfer in accordance with commands from a CPU (Central Processing Unit). Generally, with data transfer by DMA, a command (descriptor) from the CPU to the DMA chip and the data being transferred share the same bus. FIG. 1 shows a configuration example of a channel adapter having such a bus.
In FIG. 1, the host computer 1 is connected with the interface 2 of a channel adapter, and cache memory 7 is connected with a DMA chip 3 of the channel adapter. Also, a data buffer 4 for temporarily holding data being transferred is connected to the DMA chip 3, with the interface 2, DMA chip 3, and CPU 5 which issues commands to the DMA chip 3, being mutually connected by a bus 6.
With a channel adapter having such a configuration, upon a read command for data being output from the host computer 1 for example, the read command is notified to the CPU 5 via the interface 2 and the bus 6, and a command is output from the CPU 5 to the DMA chip 3 to the effect that data is to be read out from the cache memory 7. Upon receiving this command, the DMA chip 3 reads out data from the cache memory 7 and holds this in the data buffer 4. Subsequently, the DMA chip 3 notifies the CPU 5 to the effect that data readout to the data buffer has been computer, and the CPU 5 starts data transfer processing for transferring data from the data buffer 4 to the host computer 1 via the bus 6.
Now, there are cases wherein multiple DMA circuits are provided to such a DMA chip. In this case, each DMA circuit reads data out from the cache memory to the data buffer in parallel, and upon the data to be transferred to the host computer for example being hold in the data buffer and being in a transferable state, notifies the CPU to the effect that the data can be transferred. This notification is transmitted to the CPU via the bus as an interruption signal requesting interruption processing, so even in the event that the CPU performs data transfer processing relating to another DMA circuit, the CPU interrupts the data transfer processing. The CPU then reads the information relating to the transfer of data held in the DMA circuit which has transmitted to the interruption signal.
Specifically, as shown in FIG. 2, upon readout of data from the cache memory being completed at a DMA circuit within the DMA chip, an interruption signal is transmitted to the CPU via the bus (Step S1). The CPU interrupts all other processing and reads the address of the data to be transferred that is held b the DMA circuit which transmitted to the interrupt signal (step S2). This read causes the address of the data to be transferred to be transmitted from the DMA circuit to the CPU via the bus (step S3), and the CPU resumes data transfer processing.
Subsequently, upon all data transfer processing being completed, the CPU reads transfer status information held in the DMA circuit, indicating whether or not the transfer has been successfully completed (step S4). This read causes the transfer status information to be transmitted from the DMA circuit to the CPU via the bus (step S5).